Abstract
For energy-aware embedded and mobile processors, this paper proposes a new energy-effective design of the instruction fetch unit that exploits the fact that the peraccess energy consumption decreases as the cache size decreases.
| Original language | English |
|---|---|
| Title of host publication | 2008 5th IEEE Consumer Communications and Networking Conference, CCNC 2008 |
| Pages | 734-735 |
| Number of pages | 2 |
| DOIs | |
| Publication status | Published - 2008 Sep 23 |
| Event | 2008 5th IEEE Consumer Communications and Networking Conference, CCNC 2008 - Las Vegas, NV, United States Duration: 2008 Jan 10 → 2008 Jan 12 |
Other
| Other | 2008 5th IEEE Consumer Communications and Networking Conference, CCNC 2008 |
|---|---|
| Country | United States |
| City | Las Vegas, NV |
| Period | 08/1/10 → 08/1/12 |
ASJC Scopus subject areas
- Computer Networks and Communications
- Software
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Cite this
Cheol, H. K., Hwang, I., Chae, C., Choi, D., Jung, T., & Jung, S. W. (2008). Energy-effective instruction fetch unit for embedded processors. In 2008 5th IEEE Consumer Communications and Networking Conference, CCNC 2008 (pp. 734-735). [4446466] https://doi.org/10.1109/ccnc08.2007.168