Abstract
Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.
| Original language | English |
|---|---|
| Pages (from-to) | 125-137 |
| Number of pages | 13 |
| Journal | Journal of Signal Processing Systems |
| Volume | 58 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2010 Feb 1 |
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Keywords
- Hardware architecture
- Low power design
- Multirate system
- Polyphase channelizer
- Very large scale integration (VLSI)
ASJC Scopus subject areas
- Hardware and Architecture
- Information Systems
- Signal Processing
- Theoretical Computer Science
- Control and Systems Engineering
- Modelling and Simulation
Cite this
Energy-efficient hardware architecture and VLSI implementation of a polyphase channelizer with applications to subband adaptive filtering. / Wang, Yongtao; Mahmoodi, Hamid; Chiou, Lih Yih; Choo, Hunsoo; Park, Jongsun; Jeong, Woopyo; Roy, Kaushik.
In: Journal of Signal Processing Systems, Vol. 58, No. 2, 01.02.2010, p. 125-137.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Energy-efficient hardware architecture and VLSI implementation of a polyphase channelizer with applications to subband adaptive filtering
AU - Wang, Yongtao
AU - Mahmoodi, Hamid
AU - Chiou, Lih Yih
AU - Choo, Hunsoo
AU - Park, Jongsun
AU - Jeong, Woopyo
AU - Roy, Kaushik
PY - 2010/2/1
Y1 - 2010/2/1
N2 - Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.
AB - Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.
KW - Hardware architecture
KW - Low power design
KW - Multirate system
KW - Polyphase channelizer
KW - Very large scale integration (VLSI)
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U2 - 10.1007/s11265-008-0323-2
DO - 10.1007/s11265-008-0323-2
M3 - Article
VL - 58
SP - 125
EP - 137
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
SN - 1939-8018
IS - 2
ER -