Energy efficient hardware architecture of LU triangularization for MIMO receiver

Ji Woong Choi, Jungwon Lee, Byung Gueon Min, Jongsun Park

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-inputmulti-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu CMOS process, and the hardware can perform LU triangularization from 2×2 to 8×8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.

Original languageEnglish
Article number5545379
Pages (from-to)632-636
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number8
DOIs
Publication statusPublished - 2010 Aug 1

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Hardware
Computational complexity
Energy conservation

Keywords

  • Low-power very large scale integration (VLSI) design
  • LU triangularization
  • matrix decomposition
  • multi-inputmulti-output (MIMO) demodulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Energy efficient hardware architecture of LU triangularization for MIMO receiver. / Choi, Ji Woong; Lee, Jungwon; Min, Byung Gueon; Park, Jongsun.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 8, 5545379, 01.08.2010, p. 632-636.

Research output: Contribution to journalArticle

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