Abstract
An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-inputmulti-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu CMOS process, and the hardware can perform LU triangularization from 2×2 to 8×8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.
| Original language | English |
|---|---|
| Article number | 5545379 |
| Pages (from-to) | 632-636 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 57 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2010 Aug 1 |
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Keywords
- Low-power very large scale integration (VLSI) design
- LU triangularization
- matrix decomposition
- multi-inputmulti-output (MIMO) demodulation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Energy efficient hardware architecture of LU triangularization for MIMO receiver. / Choi, Ji Woong; Lee, Jungwon; Min, Byung Gueon; Park, Jongsun.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 8, 5545379, 01.08.2010, p. 632-636.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Energy efficient hardware architecture of LU triangularization for MIMO receiver
AU - Choi, Ji Woong
AU - Lee, Jungwon
AU - Min, Byung Gueon
AU - Park, Jongsun
PY - 2010/8/1
Y1 - 2010/8/1
N2 - An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-inputmulti-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu CMOS process, and the hardware can perform LU triangularization from 2×2 to 8×8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.
AB - An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-inputmulti-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu CMOS process, and the hardware can perform LU triangularization from 2×2 to 8×8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.
KW - Low-power very large scale integration (VLSI) design
KW - LU triangularization
KW - matrix decomposition
KW - multi-inputmulti-output (MIMO) demodulation
UR - http://www.scopus.com/inward/record.url?scp=77955850466&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955850466&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2010.2055991
DO - 10.1109/TCSII.2010.2055991
M3 - Article
AN - SCOPUS:77955850466
VL - 57
SP - 632
EP - 636
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 8
M1 - 5545379
ER -