Abstract
An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-inputmulti-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu CMOS process, and the hardware can perform LU triangularization from 2×2 to 8×8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.
| Original language | English |
|---|---|
| Article number | 5545379 |
| Pages (from-to) | 632-636 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 57 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2010 Aug |
Keywords
- LU triangularization
- Low-power very large scale integration (VLSI) design
- matrix decomposition
- multi-inputmulti-output (MIMO) demodulation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Choi, J. W., Lee, J., Min, B. G., & Park, J. (2010). Energy efficient hardware architecture of LU triangularization for MIMO receiver. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(8), 632-636. [5545379]. https://doi.org/10.1109/TCSII.2010.2055991