Energy-efficient skewed static logic design with dual Vt

Chulwoo Kim, Kiwook Kim, Sung Mo Steve Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S/sup 2/L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. Synthesis algorithm for S/sup 2/L developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages882-885
Number of pages4
Volume4
DOIs
Publication statusPublished - 2001 Dec 1
Externally publishedYes
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01/5/601/5/9

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Kim, C., Kim, K., & Kang, S. M. S. (2001). Energy-efficient skewed static logic design with dual Vt. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (Vol. 4, pp. 882-885). [922379] https://doi.org/10.1109/ISCAS.2001.922379