Energy-efficient Skewed Static Logic design with dual VT

Chulwoo Kim, K. Kim, S. M. Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we describe Skewed Static Logic (S 2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S 2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S 2L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S 2L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S 2L is developed and the experimental results show S 2L consumes 23% less power than MS CMOS with minor increase in delay.

Original languageEnglish
Title of host publicationMaterials Research Society Symposium - Proceedings
EditorsT.M. Tritt, G.S. Nolas, G.D. Mahan, D. Mandrus
Volume626
Publication statusPublished - 2001
Externally publishedYes
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

Other

OtherThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications
CountryUnited States
CitySan Francisco, CA
Period00/4/2400/4/27

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials

Cite this

Kim, C., Kim, K., & Kang, S. M. (2001). Energy-efficient Skewed Static Logic design with dual VT. In T. M. Tritt, G. S. Nolas, G. D. Mahan, & D. Mandrus (Eds.), Materials Research Society Symposium - Proceedings (Vol. 626)