Energy-efficient Skewed Static Logic design with dual VT

C. Kim, K. Kim, S. M. Kang

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits energy-efficient operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S2L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S2L is developed and the experimental results show S2L consumes 23% less power than MS CMOS with minor increase in delay.

Original languageEnglish
Pages (from-to)IV882-IV885
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001
Externally publishedYes
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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