Energy-efficient skewed static logic with dual Vt

Design and synthesis

Chulwoo Kim, Ki Wook Kim, Sung Mo Kang

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

In this paper, we describe skewed static logic (S2 L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S2 L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S2 L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-μm CMOS technology and verified that S2 L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S2 L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S2 L is developed and the experimental results show S2 L consumes 23% less power than MS CMOS with minor increase in delay.

Original languageEnglish
Pages (from-to)64-70
Number of pages7
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume11
Issue number1
DOIs
Publication statusPublished - 2003 Feb 1

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Networks (circuits)
Adders
Particle accelerators
Topology
Degradation

Keywords

  • Accelerator
  • Adder
  • Dual Vt
  • Low power
  • Skewed logic
  • Synthesis algorithm

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Energy-efficient skewed static logic with dual Vt : Design and synthesis. / Kim, Chulwoo; Kim, Ki Wook; Kang, Sung Mo.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 1, 01.02.2003, p. 64-70.

Research output: Contribution to journalArticle

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