Energy-efficient soft error-tolerant digital signal processing

Byonghyo Shim, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review

90 Citations (Scopus)


In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques-spatial, temporal and spatio-temporal-are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to P er = 10 -2 and P er = 10 -3 in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNR des = 25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.

Original languageEnglish
Article number1637464
Pages (from-to)336-348
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 2006 Apr


  • Digital signal processing (DSP)
  • Low-power
  • Reduced precision redundancy (RPR)
  • Reliability
  • Soft error tolerance
  • Triple modular redundancy (TMR)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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