Abstract
The effects of a metal-interlayer-semiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. When the MIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal-semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node.
Original language | English |
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Article number | 9384164 |
Pages (from-to) | 2275-2280 |
Number of pages | 6 |
Journal | IEEE Transactions on Electron Devices |
Volume | 68 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2021 May |
Keywords
- 3-D technology computer aided design (TCAD) simulation
- charge-sharing time
- contact resistance
- dynamic random access memory (DRAM)
- gate-induced drain leakage (GIDL)
- metal-interlayer-semiconductor (MIS)
- retention time
- write time
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering