Abstract
Recent studies have shown that embedded DRAM (eDRAM) is a promising approach for 3D stacked last-level caches (LLCs) rather than SRAM due to its advantages over SRAM; (i) eDRAM occupies less area than SRAM due to its smaller bit cell size; and (ii) eDRAM has much less leakage power and access energy than SRAM, since it has much smaller number of transistors than SRAM. However, different from SRAM cells, eDRAM cells should be refreshed periodically in order to retain the data. Since refresh operations consume noticeable amount of energy, it is important to adopt appropriate refresh interval, which is highly dependent on the temperature. However, the conventional refresh method assumes the worst-case temperature for all eDRAM stacked cache banks, resulting in unnecessarily frequent refresh operations. In this paper, we propose a novel temperature-aware refresh scheme for 3D stacked eDRAM caches. Our proposed scheme dynamically changes refresh interval depending on the temperature of eDRAM stacked last-level cache (LLC). Compared to the conventional refresh method, our proposed scheme reduces the number of refresh operations of the eDRAM stacked LLC by 28.5% (on 32. MB eDRAM LLC), on average, with small area overhead. Consequently, our proposed scheme reduces the overall eDRAM LLC energy consumption by 12.5% (on 32. MB eDRAM LLC), on average.
| Original language | English |
|---|---|
| Journal | Microprocessors and Microsystems |
| DOIs | |
| Publication status | Accepted/In press - 2014 Aug 26 |
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Keywords
- 3D Microprocessors
- Cache
- EDRAM
- Refresh interval
- Temperature
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Software
- Artificial Intelligence
Cite this
Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches. / Gong, Young Ho; Kim, Jae Min; Lim, Sung Kyu; Jung, Sung Woo.
In: Microprocessors and Microsystems, 26.08.2014.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches
AU - Gong, Young Ho
AU - Kim, Jae Min
AU - Lim, Sung Kyu
AU - Jung, Sung Woo
PY - 2014/8/26
Y1 - 2014/8/26
N2 - Recent studies have shown that embedded DRAM (eDRAM) is a promising approach for 3D stacked last-level caches (LLCs) rather than SRAM due to its advantages over SRAM; (i) eDRAM occupies less area than SRAM due to its smaller bit cell size; and (ii) eDRAM has much less leakage power and access energy than SRAM, since it has much smaller number of transistors than SRAM. However, different from SRAM cells, eDRAM cells should be refreshed periodically in order to retain the data. Since refresh operations consume noticeable amount of energy, it is important to adopt appropriate refresh interval, which is highly dependent on the temperature. However, the conventional refresh method assumes the worst-case temperature for all eDRAM stacked cache banks, resulting in unnecessarily frequent refresh operations. In this paper, we propose a novel temperature-aware refresh scheme for 3D stacked eDRAM caches. Our proposed scheme dynamically changes refresh interval depending on the temperature of eDRAM stacked last-level cache (LLC). Compared to the conventional refresh method, our proposed scheme reduces the number of refresh operations of the eDRAM stacked LLC by 28.5% (on 32. MB eDRAM LLC), on average, with small area overhead. Consequently, our proposed scheme reduces the overall eDRAM LLC energy consumption by 12.5% (on 32. MB eDRAM LLC), on average.
AB - Recent studies have shown that embedded DRAM (eDRAM) is a promising approach for 3D stacked last-level caches (LLCs) rather than SRAM due to its advantages over SRAM; (i) eDRAM occupies less area than SRAM due to its smaller bit cell size; and (ii) eDRAM has much less leakage power and access energy than SRAM, since it has much smaller number of transistors than SRAM. However, different from SRAM cells, eDRAM cells should be refreshed periodically in order to retain the data. Since refresh operations consume noticeable amount of energy, it is important to adopt appropriate refresh interval, which is highly dependent on the temperature. However, the conventional refresh method assumes the worst-case temperature for all eDRAM stacked cache banks, resulting in unnecessarily frequent refresh operations. In this paper, we propose a novel temperature-aware refresh scheme for 3D stacked eDRAM caches. Our proposed scheme dynamically changes refresh interval depending on the temperature of eDRAM stacked last-level cache (LLC). Compared to the conventional refresh method, our proposed scheme reduces the number of refresh operations of the eDRAM stacked LLC by 28.5% (on 32. MB eDRAM LLC), on average, with small area overhead. Consequently, our proposed scheme reduces the overall eDRAM LLC energy consumption by 12.5% (on 32. MB eDRAM LLC), on average.
KW - 3D Microprocessors
KW - Cache
KW - EDRAM
KW - Refresh interval
KW - Temperature
UR - http://www.scopus.com/inward/record.url?scp=84968324813&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84968324813&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2016.01.010
DO - 10.1016/j.micpro.2016.01.010
M3 - Article
AN - SCOPUS:84968324813
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
SN - 0141-9331
ER -