Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

Cong Thuan Do, Young Ho Gong, Cheol Hong Kim, Seon Wook Kim, Sung Woo Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The warp scheduler plays an important role in the GPU for efficient utilization of hardware resources. However, the efficiency of the warp scheduler is often limited by the L1 cache (especially, L1 data cache) capacity; providing large capacity for an L1 cache is challenging due to the increased latency. In this paper, we adopt Monolithic 3D (M3D) technology to design a large capacity L1 cache for GPU performance enhancement, not deteriorating the latency. Our evaluation results show that the M3D L1 cache improves GPU performance by 2.18~2.24× on average, compared to the 2D conventional L1 cache.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, ISLPED 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728129549
DOIs
Publication statusPublished - 2019 Jul
Event2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 - Lausanne, Switzerland
Duration: 2019 Jul 292019 Jul 31

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2019-July
ISSN (Print)1533-4678

Conference

Conference2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
CountrySwitzerland
CityLausanne
Period19/7/2919/7/31

Keywords

  • GPGPU
  • Monolithic 3D
  • Warp Scheduling

ASJC Scopus subject areas

  • Engineering(all)

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