TY - GEN
T1 - Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter
AU - Jeong, Jinho
AU - Park, Jongsun
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - To overcome the von-Neumann bottleneck, static random-Access memory (SRAM)-based in-memory computing (IMC) which enables parallel data processing in the memory, is being researched. To prevent the read disturbance issue, conventional 6T SRAM IMC employs Word-Line Under-Drive (WLUD), which leads to slow bit-line (BL) computing. Another approach to cope with the read disturbance is to use 10T SRAM cells in which BLs are decoupled for read and write operation. However, the overhead in the bit-cell array density is not affordable. In this paper, a fast 6T SRAM BL computing technique that prevents the read disturbance issue is proposed. The proposed technique adopts two consecutive short pulse WLs to avoid read disturbance, and skewed-inverter-based sense amplifiers to achieve the fast BL computation. A feedback loop for faster BL computing is also proposed. 128 × 128 IMC architecture is implemented using a 28nm CMOS process, and the delay of BL computing is improved 0.354X compared to WLUD in the worst case.
AB - To overcome the von-Neumann bottleneck, static random-Access memory (SRAM)-based in-memory computing (IMC) which enables parallel data processing in the memory, is being researched. To prevent the read disturbance issue, conventional 6T SRAM IMC employs Word-Line Under-Drive (WLUD), which leads to slow bit-line (BL) computing. Another approach to cope with the read disturbance is to use 10T SRAM cells in which BLs are decoupled for read and write operation. However, the overhead in the bit-cell array density is not affordable. In this paper, a fast 6T SRAM BL computing technique that prevents the read disturbance issue is proposed. The proposed technique adopts two consecutive short pulse WLs to avoid read disturbance, and skewed-inverter-based sense amplifiers to achieve the fast BL computation. A feedback loop for faster BL computing is also proposed. 128 × 128 IMC architecture is implemented using a 28nm CMOS process, and the delay of BL computing is improved 0.354X compared to WLUD in the worst case.
KW - Bitline Computing
KW - In-Memory Computing
KW - Read Disturb
KW - Short Pulse WL
UR - http://www.scopus.com/inward/record.url?scp=85100763840&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9333058
DO - 10.1109/ISOCC50952.2020.9333058
M3 - Conference contribution
AN - SCOPUS:85100763840
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 292
EP - 293
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -