Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

I. J. Chang, J. Park, K. Kang, K. Roy

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named 'critical point sampling'. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being ∼50× faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.

Original languageEnglish
Pages (from-to)469-478
Number of pages10
JournalIET Circuits, Devices and Systems
Volume4
Issue number6
DOIs
Publication statusPublished - 2010 Nov

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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