Fast VLSI motion estimator based on bit plane matching

Y. K. Ko, H. G. Kim, H. C. Oh, S. J. Ko

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.

Original languageEnglish
Pages (from-to)1923-1924
Number of pages2
JournalElectronics Letters
Volume36
Issue number23
DOIs
Publication statusPublished - 2000 Nov 9

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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