Fast VLSI motion estimator based on bit plane matching

Y. K. Ko, H. G. Kim, H. C. Oh, Sung-Jea Ko

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.

Original languageEnglish
Pages (from-to)1923-1924
Number of pages2
JournalElectronics Letters
Volume36
Issue number23
DOIs
Publication statusPublished - 2000 Nov 9

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Data storage equipment
Shift registers
Static random access storage
Processing
Fabrication
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Fast VLSI motion estimator based on bit plane matching. / Ko, Y. K.; Kim, H. G.; Oh, H. C.; Ko, Sung-Jea.

In: Electronics Letters, Vol. 36, No. 23, 09.11.2000, p. 1923-1924.

Research output: Contribution to journalArticle

Ko, Y. K. ; Kim, H. G. ; Oh, H. C. ; Ko, Sung-Jea. / Fast VLSI motion estimator based on bit plane matching. In: Electronics Letters. 2000 ; Vol. 36, No. 23. pp. 1923-1924.
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