Abstract
We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (~2 × 10<sup>18</sup> cm<sup>-3</sup>) structure exhibits a ~1660× reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.
| Original language | English |
|---|---|
| Article number | 7151781 |
| Pages (from-to) | 884-886 |
| Number of pages | 3 |
| Journal | IEEE Electron Device Letters |
| Volume | 36 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 2015 Sep 1 |
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Keywords
- Fermi level unpinning
- gallium arsenide
- Specific contact resistivity
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors. / Kim, Seung Hwan; Kim, Gwang Sik; Kim, Jeong Kyu; Park, Jin Hong; Shin, Changhwan; Choi, Changhwan; Yu, Hyun-Yong.
In: IEEE Electron Device Letters, Vol. 36, No. 9, 7151781, 01.09.2015, p. 884-886.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors
AU - Kim, Seung Hwan
AU - Kim, Gwang Sik
AU - Kim, Jeong Kyu
AU - Park, Jin Hong
AU - Shin, Changhwan
AU - Choi, Changhwan
AU - Yu, Hyun-Yong
PY - 2015/9/1
Y1 - 2015/9/1
N2 - We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (~2 × 1018 cm-3) structure exhibits a ~1660× reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.
AB - We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (~2 × 1018 cm-3) structure exhibits a ~1660× reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.
KW - Fermi level unpinning
KW - gallium arsenide
KW - Specific contact resistivity
UR - http://www.scopus.com/inward/record.url?scp=84940385435&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84940385435&partnerID=8YFLogxK
U2 - 10.1109/LED.2015.2453479
DO - 10.1109/LED.2015.2453479
M3 - Article
AN - SCOPUS:84940385435
VL - 36
SP - 884
EP - 886
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 9
M1 - 7151781
ER -