Field programmable gate array-based Haar classifier for accelerating face detection algorithm

C. Gao, S. L. Lu, Taeweon Suh, Heui Seok Lim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10× and 72× speedups, respectively, over the software counterpart. Moreover, the authors', approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.

Original languageEnglish
Article numberIIPEAT000004000003000184000001
Pages (from-to)184-194
Number of pages11
JournalIET Image Processing
Volume4
Issue number3
DOIs
Publication statusPublished - 2010 Jun 1

Fingerprint

Face recognition
Field programmable gate arrays (FPGA)
Classifiers
Particle accelerators
Momentum

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Software
  • Computer Vision and Pattern Recognition

Cite this

Field programmable gate array-based Haar classifier for accelerating face detection algorithm. / Gao, C.; Lu, S. L.; Suh, Taeweon; Lim, Heui Seok.

In: IET Image Processing, Vol. 4, No. 3, IIPEAT000004000003000184000001, 01.06.2010, p. 184-194.

Research output: Contribution to journalArticle

@article{ed1ec6106f2f4173a4ab606192b210f4,
title = "Field programmable gate array-based Haar classifier for accelerating face detection algorithm",
abstract = "The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10× and 72× speedups, respectively, over the software counterpart. Moreover, the authors', approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.",
author = "C. Gao and Lu, {S. L.} and Taeweon Suh and Lim, {Heui Seok}",
year = "2010",
month = "6",
day = "1",
doi = "10.1049/iet-ipr.2009.0030",
language = "English",
volume = "4",
pages = "184--194",
journal = "IET Image Processing",
issn = "1751-9659",
publisher = "Institution of Engineering and Technology",
number = "3",

}

TY - JOUR

T1 - Field programmable gate array-based Haar classifier for accelerating face detection algorithm

AU - Gao, C.

AU - Lu, S. L.

AU - Suh, Taeweon

AU - Lim, Heui Seok

PY - 2010/6/1

Y1 - 2010/6/1

N2 - The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10× and 72× speedups, respectively, over the software counterpart. Moreover, the authors', approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.

AB - The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10× and 72× speedups, respectively, over the software counterpart. Moreover, the authors', approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.

UR - http://www.scopus.com/inward/record.url?scp=77955733883&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955733883&partnerID=8YFLogxK

U2 - 10.1049/iet-ipr.2009.0030

DO - 10.1049/iet-ipr.2009.0030

M3 - Article

AN - SCOPUS:77955733883

VL - 4

SP - 184

EP - 194

JO - IET Image Processing

JF - IET Image Processing

SN - 1751-9659

IS - 3

M1 - IIPEAT000004000003000184000001

ER -