Field programmable gate array-based Haar classifier for accelerating face detection algorithm

C. Gao, S. L. Lu, T. Suh, H. Lim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10× and 72× speedups, respectively, over the software counterpart. Moreover, the authors', approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.

Original languageEnglish
Article numberIIPEAT000004000003000184000001
Pages (from-to)184-194
Number of pages11
JournalIET Image Processing
Volume4
Issue number3
DOIs
Publication statusPublished - 2010 Jun

ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering

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