TY - GEN
T1 - Fine-pitch, cost effective flip chip package development
T2 - 60th Electronic Components and Technology Conference, ECTC 2010
AU - Park, Soojeoung
AU - Jo, Sanggui
AU - Park, Jiyong
AU - Kim, Hyonchol
AU - Bae, Kawngjin
AU - Kim, Chulwoo
AU - Choi, Kyoungsei
AU - Kang, Sayoon
N1 - Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2010
Y1 - 2010
N2 - This paper presents a cost effective fine-pitch flip chip solution to meet the increasing demand for the high performance small form factor packages. Tape Automated Bonding (TAB)-BGA package utilizes thermo-compression to bond a flip chip onto a film based substrate instead of reflow soldering. This approach allows for fine-pitch connection that can save significant substrate area, which can be especially cost effective for some package designs that can reduce the conductive layer count from 2 to 1 [1]. For second level interconnects, typical BGA approach was taken for easy adoption. Successfully implementing TAB-BGA has several technical challenges. Applying underfill under the fine-pitch flip chip without creating voids can be difficult. One way to overcome this challenge is by using no filler underfill and overmold type flip chip; however, that can potentially lead to high water absorption rate and delamination issues. Furthermore, board level reliability, especially temperature cycle, can have high failure rate for this type of single layer package structure [2]. To overcome these challenges, flexible PI film based substrate has been used to reduce the residual stress within the package. In addition, Epoxy Molding Compound (EMC) with low modulus at high temperature and solder resist stress buffer layer have been applied to improve the package and board level reliability.
AB - This paper presents a cost effective fine-pitch flip chip solution to meet the increasing demand for the high performance small form factor packages. Tape Automated Bonding (TAB)-BGA package utilizes thermo-compression to bond a flip chip onto a film based substrate instead of reflow soldering. This approach allows for fine-pitch connection that can save significant substrate area, which can be especially cost effective for some package designs that can reduce the conductive layer count from 2 to 1 [1]. For second level interconnects, typical BGA approach was taken for easy adoption. Successfully implementing TAB-BGA has several technical challenges. Applying underfill under the fine-pitch flip chip without creating voids can be difficult. One way to overcome this challenge is by using no filler underfill and overmold type flip chip; however, that can potentially lead to high water absorption rate and delamination issues. Furthermore, board level reliability, especially temperature cycle, can have high failure rate for this type of single layer package structure [2]. To overcome these challenges, flexible PI film based substrate has been used to reduce the residual stress within the package. In addition, Epoxy Molding Compound (EMC) with low modulus at high temperature and solder resist stress buffer layer have been applied to improve the package and board level reliability.
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U2 - 10.1109/ECTC.2010.5490879
DO - 10.1109/ECTC.2010.5490879
M3 - Conference contribution
AN - SCOPUS:77955201008
SN - 9781424464104
T3 - Proceedings - Electronic Components and Technology Conference
SP - 20
EP - 24
BT - 2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010
Y2 - 1 June 2010 through 4 June 2010
ER -