First-level instruction cache design for reducing dynamic energy consumption

Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Jung, Chu Shik Jhon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% - 59%.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science
EditorsT.D. Hamalainen, A.D. Pimentel, J. Takala, S. Vassiliadis
Pages103-111
Number of pages9
Volume3553
Publication statusPublished - 2005
Externally publishedYes
Event5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005 - Samos, Greece
Duration: 2005 Jul 182005 Jul 20

Other

Other5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005
CountryGreece
CitySamos
Period05/7/1805/7/20

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Energy utilization
Energy efficiency
Simulators

ASJC Scopus subject areas

  • Computer Science (miscellaneous)

Cite this

Kim, C. H., Shim, S., Kwak, J. W., Jung, S. W., & Jhon, C. S. (2005). First-level instruction cache design for reducing dynamic energy consumption. In T. D. Hamalainen, A. D. Pimentel, J. Takala, & S. Vassiliadis (Eds.), Lecture Notes in Computer Science (Vol. 3553, pp. 103-111)

First-level instruction cache design for reducing dynamic energy consumption. / Kim, Cheol Hong; Shim, Sunghoon; Kwak, Jong Wook; Jung, Sung Woo; Jhon, Chu Shik.

Lecture Notes in Computer Science. ed. / T.D. Hamalainen; A.D. Pimentel; J. Takala; S. Vassiliadis. Vol. 3553 2005. p. 103-111.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, CH, Shim, S, Kwak, JW, Jung, SW & Jhon, CS 2005, First-level instruction cache design for reducing dynamic energy consumption. in TD Hamalainen, AD Pimentel, J Takala & S Vassiliadis (eds), Lecture Notes in Computer Science. vol. 3553, pp. 103-111, 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005, Samos, Greece, 05/7/18.
Kim CH, Shim S, Kwak JW, Jung SW, Jhon CS. First-level instruction cache design for reducing dynamic energy consumption. In Hamalainen TD, Pimentel AD, Takala J, Vassiliadis S, editors, Lecture Notes in Computer Science. Vol. 3553. 2005. p. 103-111
Kim, Cheol Hong ; Shim, Sunghoon ; Kwak, Jong Wook ; Jung, Sung Woo ; Jhon, Chu Shik. / First-level instruction cache design for reducing dynamic energy consumption. Lecture Notes in Computer Science. editor / T.D. Hamalainen ; A.D. Pimentel ; J. Takala ; S. Vassiliadis. Vol. 3553 2005. pp. 103-111
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