First-level instruction cache design for reducing dynamic energy consumption

Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% - 59%.

Original languageEnglish
Pages (from-to)103-111
Number of pages9
JournalLecture Notes in Computer Science
Publication statusPublished - 2005
Externally publishedYes
Event5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005 - Samos, Greece
Duration: 2005 Jul 182005 Jul 20

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


Dive into the research topics of 'First-level instruction cache design for reducing dynamic energy consumption'. Together they form a unique fingerprint.

Cite this