Abstract
Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% - 59%.
| Original language | English |
|---|---|
| Title of host publication | Lecture Notes in Computer Science |
| Editors | T.D. Hamalainen, A.D. Pimentel, J. Takala, S. Vassiliadis |
| Pages | 103-111 |
| Number of pages | 9 |
| Volume | 3553 |
| Publication status | Published - 2005 |
| Externally published | Yes |
| Event | 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005 - Samos, Greece Duration: 2005 Jul 18 → 2005 Jul 20 |
Other
| Other | 5th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2005 |
|---|---|
| Country | Greece |
| City | Samos |
| Period | 05/7/18 → 05/7/20 |
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ASJC Scopus subject areas
- Computer Science (miscellaneous)
Cite this
First-level instruction cache design for reducing dynamic energy consumption. / Kim, Cheol Hong; Shim, Sunghoon; Kwak, Jong Wook; Jung, Sung Woo; Jhon, Chu Shik.
Lecture Notes in Computer Science. ed. / T.D. Hamalainen; A.D. Pimentel; J. Takala; S. Vassiliadis. Vol. 3553 2005. p. 103-111.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - First-level instruction cache design for reducing dynamic energy consumption
AU - Kim, Cheol Hong
AU - Shim, Sunghoon
AU - Kwak, Jong Wook
AU - Jung, Sung Woo
AU - Jhon, Chu Shik
PY - 2005
Y1 - 2005
N2 - Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% - 59%.
AB - Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% - 59%.
UR - http://www.scopus.com/inward/record.url?scp=26444541813&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=26444541813&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:26444541813
VL - 3553
SP - 103
EP - 111
BT - Lecture Notes in Computer Science
A2 - Hamalainen, T.D.
A2 - Pimentel, A.D.
A2 - Takala, J.
A2 - Vassiliadis, S.
ER -