We present a capacitor-less 1T-DRAM cell on SiO$-2$ /Si substrates using a silicon nanowire (SiNW) as the channel material. The SiNWs are fabricated by a top-down route that is fully compatible with the current Si-based CMOS technology. Based on the observation of the floating body effect of a partially depleted (PD) silicon nanowire transistor (SNWT), its 1T-DRAM functionality and reliability characteristics are investigated. By virtue of the top-down route providing a printable form of the inverted triangular SiNWs, the PD SNWT 1T-DRAM cell can be applied on insulating plastic substrates for potential applications of flexible electronics.
- floating body effect
- partially depleted (PD)
- silicon nanowire transistor (SNWT)
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications