TY - GEN
T1 - FPGA reverse engineering in Vivado design suite based on X-ray project
AU - Yu, Hoyoung
AU - Lee, Hyung Min
AU - Shin, Youngjoo
AU - Kim, Youngmin
N1 - Funding Information:
ACKNOWLEDGMENT This research was supported by the Basic Science Research Program, through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (NRF-2017R1D1A1B03028065).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10/1
Y1 - 2019/10/1
N2 - As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.
AB - As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.
KW - FPGA
KW - Non-invasive attack
KW - Reverse engineering
UR - http://www.scopus.com/inward/record.url?scp=85087824365&partnerID=8YFLogxK
U2 - 10.1109/ISOCC47750.2019.9078504
DO - 10.1109/ISOCC47750.2019.9078504
M3 - Conference contribution
AN - SCOPUS:85087824365
T3 - Proceedings - 2019 International SoC Design Conference, ISOCC 2019
SP - 239
EP - 240
BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th International System-on-Chip Design Conference, ISOCC 2019
Y2 - 6 October 2019 through 9 October 2019
ER -