Abstract
A buried p-layer has been successfully implemented in a fully ion implanted InP JFET for the first time. Using Be co-implanted with Si, a sharp channel profile is obtained. The saturation current has been reduced and the pinch-off characteristic has been improved with a slight decrease in transconductance and cutoff frequency. The equivalent circuits for the JFET with and without the buried p-layer are compared.
Original language | English |
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Pages (from-to) | 57-58 |
Number of pages | 2 |
Journal | IEEE Electron Device Letters |
Volume | 11 |
Issue number | 1 |
DOIs | |
Publication status | Published - 1990 Jan |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering