Abstract
It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-κ dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.
| Original language | English |
|---|---|
| Title of host publication | ECS Transactions |
| Pages | 3-12 |
| Number of pages | 10 |
| Volume | 16 |
| Edition | 10 |
| DOIs | |
| Publication status | Published - 2008 Dec 1 |
| Externally published | Yes |
| Event | 3rd SiGe, Ge, and Related Compounds: Materials, Processing and Devices Symposium - 214th ECS Meeting - Honolulu, HI, United States Duration: 2008 Oct 12 → 2008 Oct 17 |
Other
| Other | 3rd SiGe, Ge, and Related Compounds: Materials, Processing and Devices Symposium - 214th ECS Meeting |
|---|---|
| Country | United States |
| City | Honolulu, HI |
| Period | 08/10/12 → 08/10/17 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Germanium for high performance MOSFETs and optical interconnects. / Saraswat, Krishna C.; Kim, Donghyun; Krishnamohan, Tejas; Kuzum, Duygii; Okyay, Ali K.; Pethe, Abhijit; Yu, Hyun-Yong.
ECS Transactions. Vol. 16 10. ed. 2008. p. 3-12.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Germanium for high performance MOSFETs and optical interconnects
AU - Saraswat, Krishna C.
AU - Kim, Donghyun
AU - Krishnamohan, Tejas
AU - Kuzum, Duygii
AU - Okyay, Ali K.
AU - Pethe, Abhijit
AU - Yu, Hyun-Yong
PY - 2008/12/1
Y1 - 2008/12/1
N2 - It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-κ dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.
AB - It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-κ dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.
UR - http://www.scopus.com/inward/record.url?scp=63149105309&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=63149105309&partnerID=8YFLogxK
U2 - 10.1149/1.2986748
DO - 10.1149/1.2986748
M3 - Conference contribution
SN - 9781566776561
VL - 16
SP - 3
EP - 12
BT - ECS Transactions
ER -