Global bus design of a bus-based COMA multiprocessor DICE

Kyung Ho Lee, Bland Quattlebaum, Sangyeun Cho, Larry Kinney

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further DICE tries to optimize the COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the `last memory block' problem on replacement. In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Futurebus+standard backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of the COMA and the little design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor such as DICE can become a viable candidate for future shared-bus multiprocessor designs.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages231-240
Number of pages10
Publication statusPublished - 1996 Dec 1
Externally publishedYes
EventProceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA
Duration: 1996 Oct 71996 Oct 9

Other

OtherProceedings of the 1996 International Conference on Computer Design, ICCD'96
CityAustin, TX, USA
Period96/10/796/10/9

Fingerprint

Memory architecture
Microprocessor chips
Scalability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, K. H., Quattlebaum, B., Cho, S., & Kinney, L. (1996). Global bus design of a bus-based COMA multiprocessor DICE. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 231-240). Piscataway, NJ, United States: IEEE.

Global bus design of a bus-based COMA multiprocessor DICE. / Lee, Kyung Ho; Quattlebaum, Bland; Cho, Sangyeun; Kinney, Larry.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Piscataway, NJ, United States : IEEE, 1996. p. 231-240.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, KH, Quattlebaum, B, Cho, S & Kinney, L 1996, Global bus design of a bus-based COMA multiprocessor DICE. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, Piscataway, NJ, United States, pp. 231-240, Proceedings of the 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA, 96/10/7.
Lee KH, Quattlebaum B, Cho S, Kinney L. Global bus design of a bus-based COMA multiprocessor DICE. In Anon, editor, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Piscataway, NJ, United States: IEEE. 1996. p. 231-240
Lee, Kyung Ho ; Quattlebaum, Bland ; Cho, Sangyeun ; Kinney, Larry. / Global bus design of a bus-based COMA multiprocessor DICE. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. Piscataway, NJ, United States : IEEE, 1996. pp. 231-240
@inproceedings{19e33804d2ab4a3fa08f38a3e5fa876e,
title = "Global bus design of a bus-based COMA multiprocessor DICE",
abstract = "DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further DICE tries to optimize the COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the `last memory block' problem on replacement. In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Futurebus+standard backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of the COMA and the little design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor such as DICE can become a viable candidate for future shared-bus multiprocessor designs.",
author = "Lee, {Kyung Ho} and Bland Quattlebaum and Sangyeun Cho and Larry Kinney",
year = "1996",
month = "12",
day = "1",
language = "English",
pages = "231--240",
editor = "Anon",
booktitle = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
publisher = "IEEE",

}

TY - GEN

T1 - Global bus design of a bus-based COMA multiprocessor DICE

AU - Lee, Kyung Ho

AU - Quattlebaum, Bland

AU - Cho, Sangyeun

AU - Kinney, Larry

PY - 1996/12/1

Y1 - 1996/12/1

N2 - DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further DICE tries to optimize the COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the `last memory block' problem on replacement. In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Futurebus+standard backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of the COMA and the little design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor such as DICE can become a viable candidate for future shared-bus multiprocessor designs.

AB - DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further DICE tries to optimize the COMA for a shared-bus medium, in particular to reduce detrimental effects of the cache coherence and the `last memory block' problem on replacement. In this paper, we present a global bus design for a bus-based COMA multiprocessor using the IEEE Futurebus+standard backplane bus and the Texas Instruments chip-set. Our design demonstrates that necessary bus transactions for DICE can be done efficiently with existing standard bus signals. Considering the benefits of the COMA and the little design complexity it adds to the conventional shared-bus multiprocessor design, a bus-based COMA multiprocessor such as DICE can become a viable candidate for future shared-bus multiprocessor designs.

UR - http://www.scopus.com/inward/record.url?scp=0030389411&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030389411&partnerID=8YFLogxK

M3 - Conference contribution

SP - 231

EP - 240

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

A2 - Anon, null

PB - IEEE

CY - Piscataway, NJ, United States

ER -