Abstract
This paper proposes a high-speed and low latency QR decomposition (QRD) architecture. In the proposed QRD architecture, two QRD algorihms, the CORDIC-based algorithm and Gram-Schmidt, is effectively combined together to reduce hardware latency. The experimental results show that the proposed architecture implemented with Samsung 0.13 um technology achieves 16.7 % speed-up over the conventional Givens rotation-based architecture with only 5.9% area overhead for 4 × 4 matrix decomposition.
Original language | English |
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Title of host publication | ISOCC 2014 - International SoC Design Conference |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 264-265 |
Number of pages | 2 |
ISBN (Print) | 9781479951260 |
DOIs | |
Publication status | Published - 2015 Apr 16 |
Event | 11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 2014 Nov 3 → 2014 Nov 6 |
Other
Other | 11th International SoC Design Conference, ISOCC 2014 |
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Country | Korea, Republic of |
City | Jeju |
Period | 14/11/3 → 14/11/6 |
Keywords
- Givens rotation
- Gram-schmidt
- multiple-input-multiple-output (MIMO)
- QR decomposition (QRD)
- very large scale integration (VLSI)
ASJC Scopus subject areas
- Hardware and Architecture