Gram-schmidt tailed high-throughput QR decomposition architecture for MIMO detector

Dongyeob Shin; Ji Hwan Yoon; Jongsun Park; Woong Choi

doi:10.1109/ISOCC.2014.7087639

Gram-schmidt tailed high-throughput QR decomposition architecture for MIMO detector

Dongyeob Shin, Ji Hwan Yoon, Jongsun Park, Woong Choi

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper proposes a high-speed and low latency QR decomposition (QRD) architecture. In the proposed QRD architecture, two QRD algorihms, the CORDIC-based algorithm and Gram-Schmidt, is effectively combined together to reduce hardware latency. The experimental results show that the proposed architecture implemented with Samsung 0.13 um technology achieves 16.7 % speed-up over the conventional Givens rotation-based architecture with only 5.9% area overhead for 4 × 4 matrix decomposition.

Original language	English
Title of host publication	ISOCC 2014 - International SoC Design Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	264-265
Number of pages	2
ISBN (Print)	9781479951260
DOIs	https://doi.org/10.1109/ISOCC.2014.7087639
Publication status	Published - 2015 Apr 16
Event	11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 2014 Nov 3 → 2014 Nov 6

Other

Other	11th International SoC Design Conference, ISOCC 2014
Country	Korea, Republic of
City	Jeju
Period	14/11/3 → 14/11/6

Keywords

Givens rotation
Gram-schmidt
multiple-input-multiple-output (MIMO)
QR decomposition (QRD)
very large scale integration (VLSI)

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/ISOCC.2014.7087639

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Cite this

Shin, D, Yoon, JH, Park, J & Choi, W 2015, Gram-schmidt tailed high-throughput QR decomposition architecture for MIMO detector. in ISOCC 2014 - International SoC Design Conference., 7087639, Institute of Electrical and Electronics Engineers Inc., pp. 264-265, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 14/11/3. https://doi.org/10.1109/ISOCC.2014.7087639

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abstract = "This paper proposes a high-speed and low latency QR decomposition (QRD) architecture. In the proposed QRD architecture, two QRD algorihms, the CORDIC-based algorithm and Gram-Schmidt, is effectively combined together to reduce hardware latency. The experimental results show that the proposed architecture implemented with Samsung 0.13 um technology achieves 16.7 % speed-up over the conventional Givens rotation-based architecture with only 5.9% area overhead for 4 × 4 matrix decomposition.",

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