Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme

Woong Choi, Hoonki Kim, Changnam Park, Taejoong Song, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-18
Number of pages2
Volume2018-June
ISBN (Electronic)9781538667002
DOIs
Publication statusPublished - 2018 Oct 22
Event32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
Duration: 2018 Jun 182018 Jun 22

Other

Other32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
CountryUnited States
CityHonolulu
Period18/6/1818/6/22

Fingerprint

Associative storage
Computer aided manufacturing
Macros
Electric power utilization
Capacitance
Energy utilization
FinFET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Choi, W., Kim, H., Park, C., Song, T., & Park, J. (2018). Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (Vol. 2018-June, pp. 17-18). [8502311] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502311

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. / Choi, Woong; Kim, Hoonki; Park, Changnam; Song, Taejoong; Park, Jongsun.

2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. p. 17-18 8502311.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Choi, W, Kim, H, Park, C, Song, T & Park, J 2018, Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. vol. 2018-June, 8502311, Institute of Electrical and Electronics Engineers Inc., pp. 17-18, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/6/18. https://doi.org/10.1109/VLSIC.2018.8502311
Choi W, Kim H, Park C, Song T, Park J. Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Vol. 2018-June. Institute of Electrical and Electronics Engineers Inc. 2018. p. 17-18. 8502311 https://doi.org/10.1109/VLSIC.2018.8502311
Choi, Woong ; Kim, Hoonki ; Park, Changnam ; Song, Taejoong ; Park, Jongsun. / Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. pp. 17-18
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