Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

Kyungho Shin, Woong Choi, Jongsun Park

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN)$ of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusAccepted/In press - 2017 Apr 25

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Static random access storage
Macros
Electric potential
Voltage scaling
Threshold voltage
Scalability
Transistors
Electric power utilization
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

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title = "Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling",
abstract = "This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN)$ of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.",
author = "Kyungho Shin and Woong Choi and Jongsun Park",
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AU - Choi, Woong

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N2 - This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN)$ of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.

AB - This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN)$ of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.

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