TY - GEN
T1 - Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP
AU - Lee, Heemin
AU - Jang, Sungyeong
AU - Kim, Han Yee
AU - Suh, Taeweon
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No.2019-0-00533, Research on CPU vulnerability detection and validation), and National Research Foundation of Korea under Grant NRF-2019R1A2C1088390. *Correspondence to: Taeweon Suh.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/1/13
Y1 - 2021/1/13
N2 - Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.
AB - Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.
KW - ACP
KW - Arm
KW - Cache side-channel attacks
KW - and FPGA
UR - http://www.scopus.com/inward/record.url?scp=85100819437&partnerID=8YFLogxK
U2 - 10.1109/ICOIN50884.2021.9334005
DO - 10.1109/ICOIN50884.2021.9334005
M3 - Conference contribution
AN - SCOPUS:85100819437
T3 - International Conference on Information Networking
SP - 32
EP - 35
BT - 35th International Conference on Information Networking, ICOIN 2021
PB - IEEE Computer Society
T2 - 35th International Conference on Information Networking, ICOIN 2021
Y2 - 13 January 2021 through 16 January 2021
ER -