High performance and area-efficient circuit-switched network on chip design

Phi Hung Pham, Yogendera Kumar, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.

Original languageEnglish
Title of host publicationProceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006
DOIs
Publication statusPublished - 2006 Dec 1
Event6th IEEE International Conference on Computer and Information Technology, CIT 2006 - Seoul, Korea, Republic of
Duration: 2006 Sep 202006 Sep 22

Other

Other6th IEEE International Conference on Computer and Information Technology, CIT 2006
CountryKorea, Republic of
CitySeoul
Period06/9/2006/9/22

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ASJC Scopus subject areas

  • Computer Science Applications
  • Information Systems
  • Software
  • Mathematics(all)

Cite this

Pham, P. H., Kumar, Y., & Kim, C. (2006). High performance and area-efficient circuit-switched network on chip design. In Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006 [4020005] https://doi.org/10.1109/CIT.2006.97