High performance and low power FIR filter design based on sharing multiplication

Jongsun Park; Woopyo Jeong; Hunsoo Choo; Hamid Mahmoodi-Meimand; Yongtao Wang; Kaushik Roy

doi:10.1145/566482.566485

High performance and low power FIR filter design based on sharing multiplication

Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy

Research output: Contribution to conference › Paper › peer-review

20 Citations (Scopus)

Abstract

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.

Original language	English
Pages	295-300
Number of pages	6
DOIs	https://doi.org/10.1145/566482.566485
Publication status	Published - 2002
Externally published	Yes
Event	Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: 2002 Aug 12 → 2002 Aug 14

Other

Other	Proceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey, CA
Period	02/8/12 → 02/8/14

Keywords

Computation sharing
Conditional capture flip-flop
FIR filter design
High performance and low power carry select adder

ASJC Scopus subject areas

Engineering(all)

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10.1145/566482.566485

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title = "High performance and low power FIR filter design based on sharing multiplication",

abstract = "We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.",

keywords = "Computation sharing, Conditional capture flip-flop, FIR filter design, High performance and low power carry select adder",

author = "Jongsun Park and Woopyo Jeong and Hunsoo Choo and Hamid Mahmoodi-Meimand and Yongtao Wang and Kaushik Roy",

year = "2002",

doi = "10.1145/566482.566485",

language = "English",

pages = "295--300",

note = "Proceedings of the 2002 International Symposium on Low Power Electronics and Design ; Conference date: 12-08-2002 Through 14-08-2002",

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T1 - High performance and low power FIR filter design based on sharing multiplication

AU - Park, Jongsun

AU - Jeong, Woopyo

AU - Choo, Hunsoo

AU - Mahmoodi-Meimand, Hamid

AU - Wang, Yongtao

AU - Roy, Kaushik

PY - 2002

Y1 - 2002

N2 - We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.

AB - We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.

KW - Computation sharing

KW - Conditional capture flip-flop

KW - FIR filter design

KW - High performance and low power carry select adder

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T2 - Proceedings of the 2002 International Symposium on Low Power Electronics and Design

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ER -

High performance and low power FIR filter design based on sharing multiplication

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Keywords

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