High performance and low power FIR filter design based on sharing multiplication

Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy

Research output: Contribution to conferencePaper

18 Citations (Scopus)

Abstract

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.

Original languageEnglish
Pages295-300
Number of pages6
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: 2002 Aug 122002 Aug 14

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period02/8/1202/8/14

Keywords

  • Computation sharing
  • Conditional capture flip-flop
  • FIR filter design
  • High performance and low power carry select adder

ASJC Scopus subject areas

  • Engineering(all)

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