High performance CMOS dual-modulus prescaler using selective latch technique

Se Yeob Kim, Soon Seob Lee, Soo-Won Kim, Tae Geun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages321-324
Number of pages4
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999 Jan 1
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

Fingerprint

Electric power utilization
Logic gates
Flip flop circuits
Mobile telecommunication systems

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, S. Y., Lee, S. S., Kim, S-W., & Kim, T. G. (1999). High performance CMOS dual-modulus prescaler using selective latch technique. In ICVC 1999 - 6th International Conference on VLSI and CAD (pp. 321-324). [820919] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICVC.1999.820919

High performance CMOS dual-modulus prescaler using selective latch technique. / Kim, Se Yeob; Lee, Soon Seob; Kim, Soo-Won; Kim, Tae Geun.

ICVC 1999 - 6th International Conference on VLSI and CAD. Institute of Electrical and Electronics Engineers Inc., 1999. p. 321-324 820919.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, SY, Lee, SS, Kim, S-W & Kim, TG 1999, High performance CMOS dual-modulus prescaler using selective latch technique. in ICVC 1999 - 6th International Conference on VLSI and CAD., 820919, Institute of Electrical and Electronics Engineers Inc., pp. 321-324, 6th International Conference on VLSI and CAD, ICVC 1999, Seoul, Korea, Republic of, 99/10/26. https://doi.org/10.1109/ICVC.1999.820919
Kim SY, Lee SS, Kim S-W, Kim TG. High performance CMOS dual-modulus prescaler using selective latch technique. In ICVC 1999 - 6th International Conference on VLSI and CAD. Institute of Electrical and Electronics Engineers Inc. 1999. p. 321-324. 820919 https://doi.org/10.1109/ICVC.1999.820919
Kim, Se Yeob ; Lee, Soon Seob ; Kim, Soo-Won ; Kim, Tae Geun. / High performance CMOS dual-modulus prescaler using selective latch technique. ICVC 1999 - 6th International Conference on VLSI and CAD. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 321-324
@inproceedings{7b9317672a1e42c79bc41d963d5523f0,
title = "High performance CMOS dual-modulus prescaler using selective latch technique",
abstract = "This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.",
author = "Kim, {Se Yeob} and Lee, {Soon Seob} and Soo-Won Kim and Kim, {Tae Geun}",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/ICVC.1999.820919",
language = "English",
isbn = "0780357272",
pages = "321--324",
booktitle = "ICVC 1999 - 6th International Conference on VLSI and CAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - High performance CMOS dual-modulus prescaler using selective latch technique

AU - Kim, Se Yeob

AU - Lee, Soon Seob

AU - Kim, Soo-Won

AU - Kim, Tae Geun

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

AB - This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

UR - http://www.scopus.com/inward/record.url?scp=85054321299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85054321299&partnerID=8YFLogxK

U2 - 10.1109/ICVC.1999.820919

DO - 10.1109/ICVC.1999.820919

M3 - Conference contribution

AN - SCOPUS:85054321299

SN - 0780357272

SN - 9780780357273

SP - 321

EP - 324

BT - ICVC 1999 - 6th International Conference on VLSI and CAD

PB - Institute of Electrical and Electronics Engineers Inc.

ER -