High performance CMOS dual-modulus prescaler using selective latch technique

Se Yeob Kim, Soon Seob Lee, Soo-Won Kim, Tae Geun Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages321-324
Number of pages4
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999 Jan 1
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

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ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, S. Y., Lee, S. S., Kim, S-W., & Kim, T. G. (1999). High performance CMOS dual-modulus prescaler using selective latch technique. In ICVC 1999 - 6th International Conference on VLSI and CAD (pp. 321-324). [820919] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICVC.1999.820919