High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology

Chulwoo Kim, Jaesik Lee, Kwang Hyun Baek, Eric Martina, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents S2L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S2L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages59-64
Number of pages6
Publication statusPublished - 2000 Jan 1
Externally publishedYes
Event2000 International Conference on Computer Design - Austin, TX, USA
Duration: 2000 Sep 172000 Sep 20

Other

Other2000 International Conference on Computer Design
CityAustin, TX, USA
Period00/9/1700/9/20

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Kim, C., Lee, J., Baek, K. H., Martina, E., & Kang, S. M. (2000). High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 59-64). IEEE.