High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

Chulwoo Kim, Seong Ook Jung, Kwang Hyun Baek, Sung Mo Kang

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.

Original languageEnglish
Pages (from-to)434-439
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume49
Issue number6
DOIs
Publication statusPublished - 2002 Jun 1
Externally publishedYes

Fingerprint

Networks (circuits)
Transistors
Adders
Clocks
Electric potential
Logic Synthesis

Keywords

  • Adder
  • Dynamic logic
  • Low-power
  • Skewed logic

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

Cite this

High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic. / Kim, Chulwoo; Jung, Seong Ook; Baek, Kwang Hyun; Kang, Sung Mo.

In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 6, 01.06.2002, p. 434-439.

Research output: Contribution to journalArticle

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