In spite of many outstanding studies, the hardware implementation of Advanced Encryption Standard (AES) algorithm is still challenging because of recurrent computations in Galois Field GF(28). In this paper, in order to revolution up the hardware implementation, we propose a new design of SubBytes and MixColumns in AES using constant binary matrix-vector multiplications. By employing constant binary matrices reduced to AND and XOR operations, we could promote a synthesis compiler to optimize the design more efficiently. In addition, in order to achieve higher throughput, we propose a four-stage pipelined AES architecture. Evaluations show that the proposed method improves both in term of throughput and area complexity. Our proposed design of AES achieved 3.8 Gbps throughput with about 9.8k gates and 1k flip-flops which was the highest throughput and the lowest gate count at the same time, on 180 nm CMOS technology. By applying our proposed method to SubBytes, the area complexity decreased by 8.3% while the latency was reduced by 5.5%.
- Advanced Encryption Standard (AES)
- Matrix-vector multiplication
ASJC Scopus subject areas
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence