TY - JOUR
T1 - Impact of channel width on back biasing effect in tri-gate MOSFET
AU - Park, So Jeong
AU - Jeon, Dae Young
AU - Montès, Laurent
AU - Barraud, Sylvain
AU - Kim, Gyu Tae
AU - Ghibaudo, Gérard
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning, Korea (Converging Research Center Program, 2013K000175, Global Frontier Research Program-the Center for Advanced Soft Electronics Code No. 2011-0031638) and the Korea Student Aid Foundation (KOSAF) grant funded by the Korea Government (MEST) (No. S2-2009-000-00991-1).
PY - 2014
Y1 - 2014
N2 - The impact of channel width on back biasing effect in n-type tri-gate metal-oxide semiconductor field effect transistor (MOSFET) on silicon-on-insulator (SOI) material was investigated. In narrow device (W top-eff = 20 nm), the relatively high control of front gate on overall channel leads to the reduced electrostatic coupling between back and front channels as well as the suppression of back bias effects on both channel threshold voltage and the effective mobility, compared to the planar device (Wtop-eff = 170 nm). The lower effective mobility with back bias in narrow device was attributed to poorer front channel interface, and, to significant effect of sidewall mobility. The back biasing effect in tri-gate MOSFET was successfully modeled with 2-D numerical simulation. Through the simulation, the mobility results were interpreted as the consequence of two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. The potential profile extracted from numerical simulation provides strong evidence showing different degree of electrostatic coupling in narrow device and planar device due to a relative influence of front gate bias control over channels.
AB - The impact of channel width on back biasing effect in n-type tri-gate metal-oxide semiconductor field effect transistor (MOSFET) on silicon-on-insulator (SOI) material was investigated. In narrow device (W top-eff = 20 nm), the relatively high control of front gate on overall channel leads to the reduced electrostatic coupling between back and front channels as well as the suppression of back bias effects on both channel threshold voltage and the effective mobility, compared to the planar device (Wtop-eff = 170 nm). The lower effective mobility with back bias in narrow device was attributed to poorer front channel interface, and, to significant effect of sidewall mobility. The back biasing effect in tri-gate MOSFET was successfully modeled with 2-D numerical simulation. Through the simulation, the mobility results were interpreted as the consequence of two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. The potential profile extracted from numerical simulation provides strong evidence showing different degree of electrostatic coupling in narrow device and planar device due to a relative influence of front gate bias control over channels.
KW - Back bias
KW - Channel width variation
KW - Electrostatic coupling
KW - SOI (silicon on insulator)
KW - Tri-gate MOSFET
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U2 - 10.1016/j.mee.2013.09.016
DO - 10.1016/j.mee.2013.09.016
M3 - Article
AN - SCOPUS:84887046511
VL - 114
SP - 91
EP - 97
JO - Microelectronic Engineering
JF - Microelectronic Engineering
SN - 0167-9317
ER -