Abstract
This paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| DOIs | |
| Publication status | Published - 2005 Dec 1 |
| Event | 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005 - Gammarth, Tunisia Duration: 2005 Dec 11 → 2005 Dec 14 |
Other
| Other | 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005 |
|---|---|
| Country | Tunisia |
| City | Gammarth |
| Period | 05/12/11 → 05/12/14 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Implementation of H.264/AVC baseline profile decoder for mobile video applications. / Suh, Ho Lee; Ji, Hwan Park; Kim, Seon Wook; Kim, Suki.
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. 2005. 4633535.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Implementation of H.264/AVC baseline profile decoder for mobile video applications
AU - Suh, Ho Lee
AU - Ji, Hwan Park
AU - Kim, Seon Wook
AU - Kim, Suki
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.
AB - This paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.
UR - http://www.scopus.com/inward/record.url?scp=56749097270&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=56749097270&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2005.4633535
DO - 10.1109/ICECS.2005.4633535
M3 - Conference contribution
AN - SCOPUS:56749097270
SN - 9789972611001
BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
ER -