Abstract
This paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.
| Original language | English |
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| Title of host publication | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| DOIs | |
| Publication status | Published - 2005 |
| Event | 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005 - Gammarth, Tunisia Duration: 2005 Dec 11 → 2005 Dec 14 |
Publication series
| Name | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
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Other
| Other | 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005 |
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| Country | Tunisia |
| City | Gammarth |
| Period | 05/12/11 → 05/12/14 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Suh, H. L., Ji, H. P., Seon, W. K., & Kim, S. (2005). Implementation of H.264/AVC baseline profile decoder for mobile video applications. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems [4633535] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2005.4633535