Block cipher ARIA is a cryptography consists of similar algorithm structure with AES, which was proposed for obtaining both security and hardware efficiency. In this paper, ARIA architecture implemented with hardware optimization scheme is proposed, in order to meet the increasing demand of implementing cryptographic module with low hardware cost. To optimize the substitution layer, which is the largest component among ARIA architecture, areas of S-boxes are optimized with composite field extension and applying irreducible polynomial coefficients which minimizes hardware cost of S-boxes. Datapath through the substitution layer is modified from 128bit to 32bit to minimize the number of S-boxes which constitute the substitution layer. With these optimization schemes, proposed architecture is implemented and synthesized using 65nm CMOS process, obtained 9942 GE of hardware area which is 78.43% less than previous ARIA implementation work.