Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification

Junghoon Cho, Junhyun Song, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Block cipher ARIA is a cryptography consists of similar algorithm structure with AES, which was proposed for obtaining both security and hardware efficiency. In this paper, ARIA architecture implemented with hardware optimization scheme is proposed, in order to meet the increasing demand of implementing cryptographic module with low hardware cost. To optimize the substitution layer, which is the largest component among ARIA architecture, areas of S-boxes are optimized with composite field extension and applying irreducible polynomial coefficients which minimizes hardware cost of S-boxes. Datapath through the substitution layer is modified from 128bit to 32bit to minimize the number of S-boxes which constitute the substitution layer. With these optimization schemes, proposed architecture is implemented and synthesized using 65nm CMOS process, obtained 9942 GE of hardware area which is 78.43% less than previous ARIA implementation work.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages304-305
Number of pages2
ISBN (Electronic)9781728183312
DOIs
Publication statusPublished - 2020 Oct 21
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 2020 Oct 212020 Oct 24

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of
CityYeosu
Period20/10/2120/10/24

Keywords

  • ARIA
  • Composite Field
  • S-box

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture

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