This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA(Field Programmable Gate Array) device and the FAR(False Acceptance Rate) shows five times better than the existing algorithm and the recognition speed is measured to be 100[ms/person].
|Number of pages||2|
|Journal||Digest of Technical Papers - IEEE International Conference on Consumer Electronics|
|Publication status||Published - 2000|
ASJC Scopus subject areas
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering