Improving energy efficiency in FPGA through judicious mapping of computation to embedded memory blocks

Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Field-programmable gate arrays (FPGAs) are being increasingly used as a preferred prototyping and accelerator platform for diverse application domains, such as digital signal processing (DSP), security, and real-time multimedia processing. However, mapping of these applications to FPGA typically suffers from poor energy efficiency because of high energy overhead of programmable interconnects (PI) in FPGA devices. This paper presents an energy-efficient heterogenous application mapping framework in FPGA, where the conventional application mappings to logic and DSP blocks (for DSP-enhanced FPGA devices) are combined with judicious mapping of specific computations to embedded memory blocks. A complete mapping methodology including functional decomposition, fusion, and optimal packing of operations is proposed and efficiently used to reduce the large energy overhead of PIs. Effectiveness of the proposed methodology is verified for a set of common applications using a commercial FPGA system. Experimental results show that the proposed heterogenous mapping approach achieves significant energy improvement for different input bit-widths (e.g., more than 35% of energy savings with 8 bit or smaller bit inputs compared to the corresponding mapping in configurable logic blocks). For further reduction of energy, we propose an energy/accuracy tradeoff approach, where the input operand bit-width is dynamically truncated to reduce memory area and energy at the expense of modest degradation in output-accuracy. We show that using a preferential truncation method, up to 88.6% energy savings can be achieved in a 32-tap finite impulse response filter with modest impact on the filter performance.

Original languageEnglish
Article number6573396
Pages (from-to)1314-1327
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number6
DOIs
Publication statusPublished - 2014 Jan 1

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Energy efficiency
Field programmable gate arrays (FPGA)
Data storage equipment
Digital signal processing
Energy conservation
FIR filters
Particle accelerators
Fusion reactions
Decomposition
Degradation
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

Improving energy efficiency in FPGA through judicious mapping of computation to embedded memory blocks. / Ghosh, Anandaroop; Paul, Somnath; Park, Jongsun; Bhunia, Swarup.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 6, 6573396, 01.01.2014, p. 1314-1327.

Research output: Contribution to journalArticle

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