Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Taeweon Suh; Hsien Hsin S. Lee; Douglas M. Blough

doi:10.1109/MM.2004.33

Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Taeweon Suh, Hsien Hsin S. Lee, Douglas M. Blough

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.

Original language	English
Pages (from-to)	33-41
Number of pages	9
Journal	IEEE Micro
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/MM.2004.33
Publication status	Published - 2004 Jul
Externally published	Yes

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2004.33

Cite this

@article{87fe9fec4ec14244a4bedd0b17b557c0,

title = "Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1",

abstract = "The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.",

author = "Taeweon Suh and Lee, {Hsien Hsin S.} and Blough, {Douglas M.}",

year = "2004",

month = jul,

doi = "10.1109/MM.2004.33",

language = "English",

volume = "24",

pages = "33--41",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "4",

}

TY - JOUR

T1 - Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

AU - Suh, Taeweon

AU - Lee, Hsien Hsin S.

AU - Blough, Douglas M.

PY - 2004/7

Y1 - 2004/7

N2 - The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.

AB - The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.

UR - http://www.scopus.com/inward/record.url?scp=4644239556&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4644239556&partnerID=8YFLogxK

U2 - 10.1109/MM.2004.33

DO - 10.1109/MM.2004.33

M3 - Article

AN - SCOPUS:4644239556

VL - 24

SP - 33

EP - 41

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 4

ER -

Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Abstract

ASJC Scopus subject areas

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