Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Taeweon Suh; Hsien Hsin S. Lee; Douglas M. Blough

doi:10.1109/MM.2004.33

Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Taeweon Suh, Hsien Hsin S. Lee, Douglas M. Blough

Research output: Contribution to journal › Article

8 Citations (Scopus)

Abstract

The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.

Original language	English
Pages (from-to)	33-41
Number of pages	9
Journal	IEEE Micro
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/MM.2004.33
Publication status	Published - 2004 Jul
Externally published	Yes

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MM.2004.33

Cite this

Suh, T., Lee, H. H. S., & Blough, D. M. (2004). Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1. IEEE Micro, 24(4), 33-41. https://doi.org/10.1109/MM.2004.33

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