Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 1

Taeweon Suh, Hsien Hsin S Lee, Douglas M. Blough

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.

Original languageEnglish
Pages (from-to)33-41
Number of pages9
JournalIEEE Micro
Volume24
Issue number4
DOIs
Publication statusPublished - 2004 Jul 1
Externally publishedYes

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Software

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