Abstract
The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.
Original language | English |
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Pages (from-to) | 33-41 |
Number of pages | 9 |
Journal | IEEE Micro |
Volume | 24 |
Issue number | 4 |
DOIs | |
Publication status | Published - 2004 Jul |
Externally published | Yes |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering