The design complexity of integrating heterogeneous processors on SoCs is not trivial. Specifically, it introduces problems in both design and validation because of the various bus interfaces and incompatible cache coherence protocols. In this paper, cache coherence issues for heterogeneous multiprocessor SoCs are covered. Topics discussed include cache coherence, lock mechanisms, and real-time operating systems (RTOS) for heterogeneous multiprocessor systems.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering