Integrating networks and memory hierarchies in a multicomputer node architecture

Lynn Choi, Andrew A. Chien

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a new multicomputer node architecture, the DI-multicomputer, which can provide higher memory and communication performance than existing multicomputer architectures. By integrating a router onto each processor chip and eliminating the memory bus interface, each processor uses packet routing for both local memory access and internode communication. Multi-packet handling mechanisms are used to implement a high performance memory interface based on packet routing. And the DI-multicomputer network interface directs different types of messages to an appropriate level of the memory hierarchy, providing efficient communication for both short and long messages. Trace-driven simulations show that the communication mechanisms of the DI-multicomputer can achieve up to four times speedup when compared to existing architectures.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages10-17
Number of pages8
ISBN (Print)0818656026
Publication statusPublished - 1994 Jan 1
Externally publishedYes
EventProceedings of the 8th International Parallel Processing Symposium - Cancun, Mex
Duration: 1994 Apr 261994 Apr 29

Other

OtherProceedings of the 8th International Parallel Processing Symposium
CityCancun, Mex
Period94/4/2694/4/29

Fingerprint

Data storage equipment
Interfaces (computer)
Communication
Program processors
Routers

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Choi, L., & Chien, A. A. (1994). Integrating networks and memory hierarchies in a multicomputer node architecture. In Proceedings of the International Conference on Parallel Processing (pp. 10-17). Piscataway, NJ, United States: Publ by IEEE.

Integrating networks and memory hierarchies in a multicomputer node architecture. / Choi, Lynn; Chien, Andrew A.

Proceedings of the International Conference on Parallel Processing. Piscataway, NJ, United States : Publ by IEEE, 1994. p. 10-17.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Choi, L & Chien, AA 1994, Integrating networks and memory hierarchies in a multicomputer node architecture. in Proceedings of the International Conference on Parallel Processing. Publ by IEEE, Piscataway, NJ, United States, pp. 10-17, Proceedings of the 8th International Parallel Processing Symposium, Cancun, Mex, 94/4/26.
Choi L, Chien AA. Integrating networks and memory hierarchies in a multicomputer node architecture. In Proceedings of the International Conference on Parallel Processing. Piscataway, NJ, United States: Publ by IEEE. 1994. p. 10-17
Choi, Lynn ; Chien, Andrew A. / Integrating networks and memory hierarchies in a multicomputer node architecture. Proceedings of the International Conference on Parallel Processing. Piscataway, NJ, United States : Publ by IEEE, 1994. pp. 10-17
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