Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate

Extraction and compact model

Faraz Najam, Yun Seop Yu, Keun Hwi Cho, Kyoung Hwan Yeo, Dong Won Kim, Jong Seung Hwang, Sangsig Kim, Sung Woo Hwang

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

Original languageEnglish
Article number6548055
Pages (from-to)2457-2463
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume60
Issue number8
DOIs
Publication statusPublished - 2013 Aug 5

Fingerprint

Silicon
Field effect transistors
Nanowires
Drain current
Charge distribution
Surface potential
MOSFET devices
Current voltage characteristics
Polysilicon

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate : Extraction and compact model. / Najam, Faraz; Yu, Yun Seop; Cho, Keun Hwi; Yeo, Kyoung Hwan; Kim, Dong Won; Hwang, Jong Seung; Kim, Sangsig; Hwang, Sung Woo.

In: IEEE Transactions on Electron Devices, Vol. 60, No. 8, 6548055, 05.08.2013, p. 2457-2463.

Research output: Contribution to journalArticle

Najam, Faraz ; Yu, Yun Seop ; Cho, Keun Hwi ; Yeo, Kyoung Hwan ; Kim, Dong Won ; Hwang, Jong Seung ; Kim, Sangsig ; Hwang, Sung Woo. / Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate : Extraction and compact model. In: IEEE Transactions on Electron Devices. 2013 ; Vol. 60, No. 8. pp. 2457-2463.
@article{1377a48b7c704a3ea5393f32fec21039,
title = "Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate: Extraction and compact model",
abstract = "Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.",
keywords = "(GAAMOSFET), Compact model, drain-source current, gate-all-around metal-oxide-semiconductor-field-effect-transistor, interface trap distribution",
author = "Faraz Najam and Yu, {Yun Seop} and Cho, {Keun Hwi} and Yeo, {Kyoung Hwan} and Kim, {Dong Won} and Hwang, {Jong Seung} and Sangsig Kim and Hwang, {Sung Woo}",
year = "2013",
month = "8",
day = "5",
doi = "10.1109/TED.2013.2268193",
language = "English",
volume = "60",
pages = "2457--2463",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate

T2 - Extraction and compact model

AU - Najam, Faraz

AU - Yu, Yun Seop

AU - Cho, Keun Hwi

AU - Yeo, Kyoung Hwan

AU - Kim, Dong Won

AU - Hwang, Jong Seung

AU - Kim, Sangsig

AU - Hwang, Sung Woo

PY - 2013/8/5

Y1 - 2013/8/5

N2 - Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

AB - Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

KW - (GAAMOSFET)

KW - Compact model

KW - drain-source current

KW - gate-all-around metal-oxide-semiconductor-field-effect-transistor

KW - interface trap distribution

UR - http://www.scopus.com/inward/record.url?scp=84880891976&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84880891976&partnerID=8YFLogxK

U2 - 10.1109/TED.2013.2268193

DO - 10.1109/TED.2013.2268193

M3 - Article

VL - 60

SP - 2457

EP - 2463

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 8

M1 - 6548055

ER -