Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate: Extraction and compact model

Faraz Najam, Yun Seop Yu, Keun Hwi Cho, Kyoung Hwan Yeo, Dong Won Kim, Jong Seung Hwang, Sansig Kim, Sung Woo Hwang

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

Original languageEnglish
Article number6548055
Pages (from-to)2457-2463
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume60
Issue number8
DOIs
Publication statusPublished - 2013

Keywords

  • (GAAMOSFET)
  • Compact model
  • drain-source current
  • gate-all-around metal-oxide-semiconductor-field-effect-transistor
  • interface trap distribution

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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