Abstract
In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.
| Original language | English |
|---|---|
| Article number | 074505 |
| Journal | Journal of Applied Physics |
| Volume | 112 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2012 Oct 1 |
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ASJC Scopus subject areas
- Physics and Astronomy(all)
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Investigation of vertically trapped charge locations in Cr-doped-SrTiO 3-based charge trapping memory devices. / Seo, Yujeong; Song, Min Yeong; An, Ho Myoung; Kim, Yeon Soo; Park, Bae Ho; Kim, Tae Geun.
In: Journal of Applied Physics, Vol. 112, No. 7, 074505, 01.10.2012.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Investigation of vertically trapped charge locations in Cr-doped-SrTiO 3-based charge trapping memory devices
AU - Seo, Yujeong
AU - Song, Min Yeong
AU - An, Ho Myoung
AU - Kim, Yeon Soo
AU - Park, Bae Ho
AU - Kim, Tae Geun
PY - 2012/10/1
Y1 - 2012/10/1
N2 - In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.
AB - In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.
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U2 - 10.1063/1.4757413
DO - 10.1063/1.4757413
M3 - Article
AN - SCOPUS:84867504513
VL - 112
JO - Journal of Applied Physics
JF - Journal of Applied Physics
SN - 0021-8979
IS - 7
M1 - 074505
ER -