Investigation of vertically trapped charge locations in Cr-doped-SrTiO ₃-based charge trapping memory devices

In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO ₃ (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO ₃/Si ₃N ₄ interface to the bulk region of Si ₃N ₄ with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO ₃/Si ₃N ₄ interface by hole injection from the Si substrate into the Si ₃N ₄ layer at a high electric field (E _OX > 7 MV/cm). In addition, some of these charges passing across the SiO ₂ (OX) layer generate many Si-SiO ₂ interface traps (D _it: 1.58 × 10 ¹² cm ^-2 eV ^-1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.