Key Length Reconfigurable ARIA Hardware with S-box Optimization

Junhyun Song, Junghoon Cho, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.

Original languageEnglish
Title of host publication2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728191614
DOIs
Publication statusPublished - 2021 Jan 31
Event2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 - Jeju, Korea, Republic of
Duration: 2021 Jan 312021 Feb 3

Publication series

Name2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Conference

Conference2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
CountryKorea, Republic of
CityJeju
Period21/1/3121/2/3

Keywords

  • ARIA
  • Composite field
  • Key length reconfigurable
  • S-box

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Information Systems
  • Information Systems and Management
  • Electrical and Electronic Engineering
  • Instrumentation

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