Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

Jang Sik Lee, Jinhan Cho, Chiyoung Lee, Inpyo Kim, Jeongju Park, Yong Mu Kim, Hyunjung Shin, Jaegab Lee, Frank Caruso

Research output: Contribution to journalArticle

216 Citations (Scopus)

Abstract

We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/ poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the 'programmed' and 'erased' states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 × 1012 cm-2 in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

Original languageEnglish
Pages (from-to)790-795
Number of pages6
JournalNature Nanotechnology
Volume2
Issue number12
DOIs
Publication statusPublished - 2007 Dec 1
Externally publishedYes

Fingerprint

Gold
Electronic properties
Nanoparticles
traps
gold
Polyelectrolytes
Data storage equipment
Equipment and Supplies
nanoparticles
electronics
Allylamine
Hafnium oxides
hafnium oxides
Flash memory
Multilayer films
Silicon
programming
Platinum
Computer programming
Carrier concentration

ASJC Scopus subject areas

  • Bioengineering
  • Biomedical Engineering
  • Materials Science(all)
  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Atomic and Molecular Physics, and Optics

Cite this

Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. / Lee, Jang Sik; Cho, Jinhan; Lee, Chiyoung; Kim, Inpyo; Park, Jeongju; Kim, Yong Mu; Shin, Hyunjung; Lee, Jaegab; Caruso, Frank.

In: Nature Nanotechnology, Vol. 2, No. 12, 01.12.2007, p. 790-795.

Research output: Contribution to journalArticle

Lee, JS, Cho, J, Lee, C, Kim, I, Park, J, Kim, YM, Shin, H, Lee, J & Caruso, F 2007, 'Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties', Nature Nanotechnology, vol. 2, no. 12, pp. 790-795. https://doi.org/10.1038/nnano.2007.380
Lee, Jang Sik ; Cho, Jinhan ; Lee, Chiyoung ; Kim, Inpyo ; Park, Jeongju ; Kim, Yong Mu ; Shin, Hyunjung ; Lee, Jaegab ; Caruso, Frank. / Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. In: Nature Nanotechnology. 2007 ; Vol. 2, No. 12. pp. 790-795.
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