Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

Eun Ae Chung, Young Pil Kim, Kab Jin Nam, Sungsam Lee, Ji Young Min, Yu Gyun Shin, Siyoung Choi, Gyoyoung Jin, Joo Tae Moon, Sangsig Kim

Research output: Contribution to journalArticle


We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.

Original languageEnglish
Pages (from-to)219-222
Number of pages4
JournalSolid-State Electronics
Issue number1
Publication statusPublished - 2011 Feb 1



  • Cell transistor
  • Gate-controlled diode
  • Leakage current
  • RCAT

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

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