LER-induced random variation-immune effect of metal-interlayer-semiconductor source/drain structure on N-Type ge junctionless FinFETs

Seung Geun Jung, Euyjin Park, Changhwan Shin, Hyun Yong Yu

Research output: Contribution to journalArticlepeer-review

Abstract

Herein, the line-edge roughness (LER)-induced random performance variation-immune effect of metal-interlayer-semiconductor (MIS) source/drain (S/D) in 7 nm n-type Ge (n-Ge) junctionless field-effect transistors (JLFETs) were investigated by 3-D TCAD simulations. Compared to the device without MIS S/D, the n-Ge JLFET with MIS S/D could effectively reduce the Ge fin doping concentration while maintaining the performance. It was demonstrated analytically that the reduced Ge fin doping concentration of the device with MIS S/D, compared to the device without MIS S/D, decreased the LER-induced random performance variations of the n-Ge JLFET; the standard deviations were reduced to 0.0318 V for Vth (reduced by 51.6%), 4.89 × 10-6 A/μm for Ion (reduced by 92.1%), 1.44 × 10-9 A/μm for Ioff (reduced by 93.7%), 1.27 mV/dec for SS (reduced by 23.1%), and 5.40 mV/V for drain-induced barrier lowering (DIBL) (reduced by 30.8%). In addition, LER-induced random performance variation was investigated in terms of scaling down fin widths. The results provided critical insight into the variability reduction of the 7 nm n-Ge JLFETs.

Original languageEnglish
Article number9329148
Pages (from-to)1340-1345
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume68
Issue number3
DOIs
Publication statusPublished - 2021 Mar

Keywords

  • Ge
  • interlayer (IL)
  • junctionless field-effect transistor (JLFET)
  • line-edge roughness (LERs)
  • random performance variation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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