Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme

Woong Choi; Kyeongho Lee; Jongsun Park

doi:10.1109/ISCAS.2018.8351461

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme

Woong Choi, Kyeongho Lee, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents an adaptive match-line (ML) discharging scheme for low power and high speed ternary content addressable memory (TCAM). In the proposed TCAM, by employing the gated ML pulldown path and ML boosting scheme, the redundant ML discharging and SL switching are eliminated while improving the search speed. By considering the number of mismatch and ML discharging speed, the ML discharging is adaptively controlled in the proposed TCAM. The simulation results with the 65nm CMOS technology show that the proposed adaptive ML discharging scheme improves up to 19% of sensing delay and saves 81% of ML power compared to the conventional approach. When compared with the state-of-the-art work, the post-layout simulations show 10% improvement of FOM (energy/bit/search).

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2018-May
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351461
Publication status	Published - 2018 Apr 26
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: 2018 May 27 → 2018 May 30

Other

Other	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country	Italy
City	Florence
Period	18/5/27 → 18/5/30

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Keywords

adaptive sensing
CAM
content addressable memory
memory
reference voltage
sensing margin
TCAM

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Choi, W., Lee, K., & Park, J. (2018). Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings (Vol. 2018-May). [8351461] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351461

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. / Choi, Woong; Lee, Kyeongho; Park, Jongsun.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. 8351461.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, W, Lee, K & Park, J 2018, Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. vol. 2018-May, 8351461, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 18/5/27. https://doi.org/10.1109/ISCAS.2018.8351461

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AB - This paper presents an adaptive match-line (ML) discharging scheme for low power and high speed ternary content addressable memory (TCAM). In the proposed TCAM, by employing the gated ML pulldown path and ML boosting scheme, the redundant ML discharging and SL switching are eliminated while improving the search speed. By considering the number of mismatch and ML discharging speed, the ML discharging is adaptively controlled in the proposed TCAM. The simulation results with the 65nm CMOS technology show that the proposed adaptive ML discharging scheme improves up to 19% of sensing delay and saves 81% of ML power compared to the conventional approach. When compared with the state-of-the-art work, the post-layout simulations show 10% improvement of FOM (energy/bit/search).

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Access to Document

10.1109/ISCAS.2018.8351461