Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter

Jinwoo Kim, Moo Young Kim, Ho Kyu Lee, Inhwa Jung, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A 6-bit, 1.6-GS/s, flash ADC with a low-power architecture is presented. The proposed low-power architecture based on an analog input pre-processing method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit, flash ADC. The advantages of the analog input pre-processing method include the low power consumption and small area due to the reduced number of comparators. The proposed flash ADC consumes 240mW at a supply voltage of 1.8V when implemented in a 0.18-μm CMOS technology. The simulated SNDR is 32dB at an input frequency of 200MHz.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs
Publication statusPublished - 2009 Sep 25
Event2009 International Conference on Consumer Electronics, ICCE 2009 - Las Vegas, NV, United States
Duration: 2009 Jan 102009 Jan 14

Other

Other2009 International Conference on Consumer Electronics, ICCE 2009
CountryUnited States
CityLas Vegas, NV
Period09/1/1009/1/14

Fingerprint

Processing
Electric power utilization
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

Kim, J., Kim, M. Y., Lee, H. K., Jung, I., & Kim, C. (2009). Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics [5012232] https://doi.org/10.1109/ICCE.2009.5012232

Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter. / Kim, Jinwoo; Kim, Moo Young; Lee, Ho Kyu; Jung, Inhwa; Kim, Chulwoo.

Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2009. 5012232.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, J, Kim, MY, Lee, HK, Jung, I & Kim, C 2009, Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter. in Digest of Technical Papers - IEEE International Conference on Consumer Electronics., 5012232, 2009 International Conference on Consumer Electronics, ICCE 2009, Las Vegas, NV, United States, 09/1/10. https://doi.org/10.1109/ICCE.2009.5012232
Kim J, Kim MY, Lee HK, Jung I, Kim C. Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2009. 5012232 https://doi.org/10.1109/ICCE.2009.5012232
Kim, Jinwoo ; Kim, Moo Young ; Lee, Ho Kyu ; Jung, Inhwa ; Kim, Chulwoo. / Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter. Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2009.
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