Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC

S. Y. Lee, Y. S. Song, J. M. Cho, S. W. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4th pipelined AU for the low-power implementation. The designed filter for 24-bit Σ□ audio DAC is fabricated with 0.18um Samsung CMOS technology.

Original languageEnglish
Title of host publication2008 Digest of Technical Papers International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008
DOIs
Publication statusPublished - 2008
Event26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008 - Las Vegas, NV, United States
Duration: 2008 Jan 92008 Jan 13

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Other

Other26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008
CountryUnited States
CityLas Vegas, NV
Period08/1/908/1/13

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Lee, S. Y., Song, Y. S., Cho, J. M., & Kim, S. W. (2008). Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. In 2008 Digest of Technical Papers International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008 [4588072] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2008.4588072