Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC

S. Y. Lee, Y. S. Song, J. M. Cho, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4 th pipelined AU for the low-power implementation. The designed filter for 24-bit Σ□ audio DAC is fabricated with 0.18um Samsung CMOS technology.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs
Publication statusPublished - 2008 Sep 23
Event26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008 - Las Vegas, NV, United States
Duration: 2008 Jan 92008 Jan 13

Other

Other26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008
CountryUnited States
CityLas Vegas, NV
Period08/1/908/1/13

Fingerprint

Random access storage
Digital filters
Frequency response

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

Cite this

Lee, S. Y., Song, Y. S., Cho, J. M., & Kim, S-W. (2008). Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics [4588072] https://doi.org/10.1109/ICCE.2008.4588072

Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. / Lee, S. Y.; Song, Y. S.; Cho, J. M.; Kim, Soo-Won.

Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2008. 4588072.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, SY, Song, YS, Cho, JM & Kim, S-W 2008, Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. in Digest of Technical Papers - IEEE International Conference on Consumer Electronics., 4588072, 26th IEEE International Conference on Consumer Electronics, The Mobile Consumer, ICCE 2008, Las Vegas, NV, United States, 08/1/9. https://doi.org/10.1109/ICCE.2008.4588072
Lee SY, Song YS, Cho JM, Kim S-W. Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. In Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2008. 4588072 https://doi.org/10.1109/ICCE.2008.4588072
Lee, S. Y. ; Song, Y. S. ; Cho, J. M. ; Kim, Soo-Won. / Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC. Digest of Technical Papers - IEEE International Conference on Consumer Electronics. 2008.
@inproceedings{f5fe3d1e786f4e00b77caa4aab5974b8,
title = "Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC",
abstract = "A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4 th pipelined AU for the low-power implementation. The designed filter for 24-bit Σ□ audio DAC is fabricated with 0.18um Samsung CMOS technology.",
author = "Lee, {S. Y.} and Song, {Y. S.} and Cho, {J. M.} and Soo-Won Kim",
year = "2008",
month = "9",
day = "23",
doi = "10.1109/ICCE.2008.4588072",
language = "English",
isbn = "142441458X",
booktitle = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

}

TY - GEN

T1 - Low-power digital filter using optimized CSD and pipelined AU for 24-bit audio DAC

AU - Lee, S. Y.

AU - Song, Y. S.

AU - Cho, J. M.

AU - Kim, Soo-Won

PY - 2008/9/23

Y1 - 2008/9/23

N2 - A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4 th pipelined AU for the low-power implementation. The designed filter for 24-bit Σ□ audio DAC is fabricated with 0.18um Samsung CMOS technology.

AB - A new optimization algorithm of the digital filter over the CSD coefficient is proposed. This method is based on the selective weighting method assigning more number of operations to some coefficients which are more sensitive to the frequency response remaining total number of operations. Also, the optimized coefficient is utilized as Control-RAM and combined with the 4 th pipelined AU for the low-power implementation. The designed filter for 24-bit Σ□ audio DAC is fabricated with 0.18um Samsung CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=51949116334&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51949116334&partnerID=8YFLogxK

U2 - 10.1109/ICCE.2008.4588072

DO - 10.1109/ICCE.2008.4588072

M3 - Conference contribution

SN - 142441458X

SN - 9781424414581

BT - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

ER -