Low power logic design using push-pull pass-transistor logics

Woo Hyun Paik, Hoon J. Ki, Soo-Won Kim

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8 μm CMOS process technology. The PPL achieves 36.4 ns delay with the power consumption of 18 mW/100 MHz in the full adder chain and 112 MHz speed with 13.4 mW/ 50 MHz power dissipation in the multiplier.

Original languageEnglish
Pages (from-to)467-478
Number of pages12
JournalInternational Journal of Electronics
Volume84
Issue number5
Publication statusPublished - 1998 Dec 1

Fingerprint

Logic design
Transistors
Adders
Energy dissipation
Electric power utilization
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Low power logic design using push-pull pass-transistor logics. / Paik, Woo Hyun; Ki, Hoon J.; Kim, Soo-Won.

In: International Journal of Electronics, Vol. 84, No. 5, 01.12.1998, p. 467-478.

Research output: Contribution to journalArticle

Paik, Woo Hyun ; Ki, Hoon J. ; Kim, Soo-Won. / Low power logic design using push-pull pass-transistor logics. In: International Journal of Electronics. 1998 ; Vol. 84, No. 5. pp. 467-478.
@article{eee96e69b2534dfdaf7b659a6643883a,
title = "Low power logic design using push-pull pass-transistor logics",
abstract = "This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8 μm CMOS process technology. The PPL achieves 36.4 ns delay with the power consumption of 18 mW/100 MHz in the full adder chain and 112 MHz speed with 13.4 mW/ 50 MHz power dissipation in the multiplier.",
author = "Paik, {Woo Hyun} and Ki, {Hoon J.} and Soo-Won Kim",
year = "1998",
month = "12",
day = "1",
language = "English",
volume = "84",
pages = "467--478",
journal = "International Journal of Electronics",
issn = "0020-7217",
publisher = "Taylor and Francis Ltd.",
number = "5",

}

TY - JOUR

T1 - Low power logic design using push-pull pass-transistor logics

AU - Paik, Woo Hyun

AU - Ki, Hoon J.

AU - Kim, Soo-Won

PY - 1998/12/1

Y1 - 1998/12/1

N2 - This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8 μm CMOS process technology. The PPL achieves 36.4 ns delay with the power consumption of 18 mW/100 MHz in the full adder chain and 112 MHz speed with 13.4 mW/ 50 MHz power dissipation in the multiplier.

AB - This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8 μm CMOS process technology. The PPL achieves 36.4 ns delay with the power consumption of 18 mW/100 MHz in the full adder chain and 112 MHz speed with 13.4 mW/ 50 MHz power dissipation in the multiplier.

UR - http://www.scopus.com/inward/record.url?scp=0000512932&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0000512932&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0000512932

VL - 84

SP - 467

EP - 478

JO - International Journal of Electronics

JF - International Journal of Electronics

SN - 0020-7217

IS - 5

ER -