A low-power programmable divider (PD) for frequency synthesiser is presented in this study. Instead of two counters used in conventional PD, a shared counter with a small control circuit is exploited in order to reduce the output load capacitance and the redundant counter operations in the divider. A novel glitchless D flip-flop is also proposed by considering the switching activities of the internal nodes of the flip-flop. The authors' proposed PD was fabricated in a standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The average power is 3.23 mW with 1.5 V supply voltage and the effective area is 0.0408 mm2. Its division ratio ranges from 13 to 1278 at 3.5 GHz. Experimental results show that the proposed divider consumes around 30% less power compared to the conventional design.
ASJC Scopus subject areas
- Control and Systems Engineering
- Electrical and Electronic Engineering